1. Field of the Invention
The present invention relates to a data conversion circuit for converting intended input data into output data using a look-up table for conversion which defines correspondence between input and output, and a technique associated with the same.
2. Description of the Background Art
In the field of image processing, output data is sometimes created by correcting input data, and in such a situation, correspondence of output data to the input data is used as correction data while referring to a reference table for data conversion which is called a look-up table (LUT: look-up table for conversion).
This look-up table is provided in an internal memory called a LUT memory (look-up table storage memory) in a digital camera, for example. In the case where input signals obtained from charge coupled devices (CCD) used in this digital camera are used in their linear characteristics, as for the dynamic range, it is difficult to completely realize ideal dynamic range because of the internal settings of the digital camera and restrictions of video output format. For this reason, signals having levels higher than the saturation level 100IRE of the RS-170 format, for example, are truncated. In such a case, for the purpose of executing the preprocessing at high speed inside the digital camera by fully using the dynamic range of the input signal, a xcex3 conversion look-up table is used.
Now referring to FIG. 9, a general xcex3 conversion look-up table 3 will be described. In the xcex3 conversion look-up table 3, memory cells (word) 8 which are in number corresponding to the number of bits of input data In are prepared, and a data size (bit depth) of each memory cell 8 corresponds to the number of bits of output data Out. In the example of FIG. 9, input data In of 10 bits is inputted and 8-bit output data is outputted. In this case, as the input data In is inputted into the xcex3 conversion look-up table 3, a value of 10 bits of this input data In (that is, 210 patterns or values of 0 to 1023: hereinafter referred to as xe2x80x9cword numberxe2x80x9d) is addressed, a memory cell 8 having the address of this value is selected, and 8-bit data of the memory cell 8 thus selected is outputted as output data Out.
Conventionally, a complete look-up table should be configured by a LUT memory, however, as shown in FIG. 10, for example, when xcex3 conversion of image data is to be conducted by using the xcex3 conversion look-up table 3 where both of the input data In and output data Out are required to be 16 bits, the word number of memory cells 8 having a bit depth of 16 bits becomes as large as 216=65536, which makes the circuit scale extremely large.
In consideration of the above, Japanese Patent Application Laid-Open No. 11-252372, for example, discloses a technique which effectively uses a look-up table. In this technique, as shown in FIG. 11, data xe2x80x9cAxe2x80x9d which is input data Din of 12-bit line and data xe2x80x9cA+1xe2x80x9d obtainable by adding xe2x80x9c1xe2x80x9d to the data xe2x80x9cAxe2x80x9d by an adder (INC) 1 are yielded, and data of upper 10-bit lines from these 12-bit line data (xe2x80x9cAxe2x80x9d/xe2x80x9cA+1xe2x80x9d) are switched by a multiplexer (MUX) 2 for outputting to three xcex3 conversion look-up tables (LUT) 3a to 3c for three colors, R, G and B. Then outputs (8-bit data) from the respective color components of these xcex3 conversion look-up tables 3a to 3c are sequentially switched and selected by a color selecting multiplexer 4, and data DA thus selected is outputted to an interpolation arithmetic circuit 5 and a latch circuit 6.
At the latch circuit 6, the data DA is latched and a resultant data DB (B=A+1) is outputted to the interpolation arithmetic circuit 5. In other words, since the data DA and the data DB are inputted to the interpolation arithmetic circuit 5 in synchronization with each other owing to the latch at the latch circuit 6, data in the xcex3 conversion look-up tables 3a to 3c is fetched in a timely-overlapped manner.
Then the interpolation arithmetic circuit 5 receives at its input, data for lower 2 bits of the input data Din (that is, 12 xe2x80x9cbitsxe2x80x9dxe2x88x9210 xe2x80x9cupper bitsxe2x80x9d) in addition to the above 8-bit data DA and DB, determines an interpolation ratio P in accordance with the data of lower 2 bits, executes the calculation of DA+(DBxe2x88x92DA)xc3x97P, and outputs the calculation result as output data Dout.
In this manner, according to the conventional technique, since a xcex3 conversion can be conducted with respect to input data whose bit number is larger than the bit depth of each memory cell (word) of the look-up table, output data Out having a sufficient bit number can be outputted even by using the LUT memories 3a to 3c having relatively small memory sizes.
Even with such a conventional technique, the bit length of output data Out is restricted by the bit depth of the respective xcex3 conversion look-up table 3a to 3c, which disabled the xcex3 conversion where the bit lengths of input and output are the same to be conducted.
In view of the above, it is an object of the present invention to provide a data conversion circuit which is able to realize a conversion output with a fineness superior to the bit depth of the LUT memory by using a LUT memory of less memory size, and related arts.
The present invention provides a data conversion circuit for converting intended input data into output data using a look-up table for conversion which defines correspondences between input and output, the data conversion circuit including: an adder for adding xe2x80x9c1xe2x80x9d to first table input data which is upper bit data having a bit length corresponding to an input format of the look-up table for conversion among the input data, to yield second table input data; a look-up table storage memory storing the look-up table for conversion, for outputting first table output data associated with the first table input data using the look-up table for conversion, as well as outputting second table output data associated with the second table input data using the same the look-up table for conversion; and a weighting operation part for performing a weighting operation on the first table output data and the second table output data based on lower bit data excluding the predetermined bit number of upper bit data among the input data, interpolating between each of the table output data, and calculating output data having a bit length which is longer than that of the first table output data and the second table output data, wherein the look-up table storage memory is a dual port memory to which the first table input data and the second table input data are inputted simultaneously, and from which the first table output data and the second table output data are outputted simultaneously.
According to this, it is possible to obtain output data with a fineness superior to the bit depth of the look-up table storage memory while reducing the bit depth and word number of the look-up table storage memory as small as possible.
In this case, since the look-up table storage memory is a dual port memory to which the first table input data and the second table input data are simultaneously inputted and from which the first table output data and the second table output data are simultaneously outputted, it is possible to efficiently input two sets of table input data and to efficiently output two sets of table output data. Therefore, it is possible to achieve efficient data conversion.
In another aspect of the present invention, there is provided a data conversion circuit for converting intended input data into output data using a look-up table for conversion which defines correspondences between input and output, the data conversion circuit including: an adder for adding xe2x80x9c1xe2x80x9d to first table input data which is upper bit data having a bit length corresponding to an input format of the look-up table for conversion among the input data, to yield second table input data; a look-up table storage memory which is a single port memory storing the look-up table for conversion, for outputting first table output data associated with the first table input data using the look-up table for conversion, as well as outputting second table output data associated with the second table input data using the same the look-up table for conversion; a weighting operation part for performing a weighting operation on the first table output data and the second table output data based on lower bit data excluding the predetermined bit number of upper bit data among the input data, interpolating between each of the table output data, and calculating output data having a bit length which is longer than that of the first table output data and the second table output data; a table input data switching part for alternately selecting the first table input data or the second table input data to be inputted to the look-up table storage memory; and a table output data switching part for alternately selecting the first table output data or the second table output data outputted from the look-up table storage memory; wherein the table output data switching part selects the first table output data in a first pulse condition within a single cycle of clock signal for synchronizing output of the output data, while selecting the second table output data in a second pulse condition within the single cycle of clock signal.
According to this, even when a single port memory which is smaller in size than a dual port memory is used as the look-up table storage memory, two sets of table input data can be individually subjected to data conversion and outputted as respective table output data. In particular, by reading out output data twice in a single cycle of clock signal from the look-up table storage memory, it is possible to prevent the rate of outputting of the output data from being affected by the interpolation process.
Preferably, the data conversion circuit further includes a delay circuit for synchronizing timing of inputting the lower bit data to the weighting operation part with an operation of the table output data switching part.
According to this, since the timing of inputting the lower bit data for the weighting operation process is synchronized with the operation of the table output data switching process by way of a delay process, the interpolation process can be executed without any problems.
In another aspect of the present invention, there is provided a data conversion circuit for converting intended input data into output data using a look-up table for conversion which defines correspondences between input and output, the data conversion circuit including: an adder for adding xe2x80x9c1xe2x80x9d to first table input data which is upper bit data having a bit length corresponding to an input format of the look-up table for conversion among the input data, to yield second table input data; an even address table storage memory configured by a single port memory, for storing a value when the value of the upper bit data among the input data is an even number; an odd address table storage memory configured by a single port memory, for storing a value when the value of the upper bit data among the input data is an odd number; a first address selector arranged at input of the even address table storage memory, for inputting the first table input data as an address of the even address table storage memory when the upper bit data is an even number, while inputting the second table input data as an address of the even address table storage memory when the upper bit data is an odd number; a second address selector arranged at input of the odd number address table storage memory, for outputting the second table input data as an address of the odd number address table storage memory when the upper bit data is an even number, while outputting the first table input data as an address of the odd number address table storage memory when the upper bit data is an odd number; a first data selector arranged at outputs of the even address table storage memory and the odd address table storage memory, for outputting output data of the even address table storage memory as first table output data when the upper bit data is an even number, while outputting output data of the odd address table storage memory as first table output data when the upper bit data is an odd number; a second data selector arranged at outputs of the even address table storage memory and the odd address table storage memory, for outputting output data of the odd address table storage memory as second table output data when the upper bit data is an even number, while outputting output data of the even address table storage memory as second table output data when the upper bit data is an odd number; and a weighting operation part for performing a weighting operation on the first table output data and the second table output data based on lower bit data excluding the predetermined bit number of upper bit data among the input data, interpolating between each of the table output data, and calculating output data.
According to this, by interleaving the even input and the odd input, only the single port memories are required, so that the circuit scale is miniaturized and the power consumption is reduced. Also, since a double-speed operation is not necessary, it is possible to suppress the operation frequency, which contributes to reduction in power consumption.
Preferably, the data conversion circuit further includes an overflow preventing part for inputting the upper bit data of the input data before subjecting to addition by the adder as the second table input data to the look-up table storage memory when the first table input data inputted to the adder and the look-up table storage memory is the maximum value, thereby preventing overflow of the second table input data.
According to this, when the first table input data inputted to the adding process and the look-up table storage memory is the maximum value, the upper bit data of the input data before subjected to addition in the adding process can be inputted to the look-up table storage memory as the second table input data, so that it is possible to efficiently prevent the second table input data from overflowing.
In another aspect of the present invention, there is provided a data conversion circuit for converting intended input data into output data using a look-up table for conversion which defines correspondences between input and output, the data conversion circuit including: an adder for adding xe2x80x9c1xe2x80x9d to first table input data which is upper bit data having a bit length corresponding to an input format of the look-up table for conversion among the input data, to yield second table input data; a look-up table storage memory storing the look-up table for conversion, for outputting first table output data associated with the first table input data using the look-up table for conversion, as well as outputting second table output data associated with the second table input data using the same the look-up table for conversion; a weighting operation part for performing a weighting operation on the first table output data and the second table output data based on lower bit data excluding the predetermined bit number of upper bit data among the input data, interpolating between each of the table output data, and calculating output data; and a specific value designating part, when the first table input data inputted to the adder and the look-up table storage memory is the maximum value, for forcefully designating a specific value preliminary determined as a value corresponding to the maximum value as the second table output data.
According to this, in the interpolation process, when the first table input data inputted to the adding process and the look-up table storage memory is the maximum value, even if the second table input data overflows due to the adding process, an ideal specific value to be used as an alternative can be forcefully and readily designated by the specific value designating process.
Preferably, the specific value is designated so that the bit length thereof is longer than that of the second table output data, the data conversion circuit further including: a bit length adjuster for adding the value xe2x80x9czeroxe2x80x9d on the lower bit side so as to coincide respective bit lengths of the first table output data and the second table output data with the bit length of the specific value.
According to this, the specific value is designated so as to have a bit length longer than that of the second table output data, and the value xe2x80x9czeroxe2x80x9d can be added on the lower bit side by the bit length adjusting process so that the bit length of the first table output data and the second table output data coincide with the bit length of the specific value. Accordingly, an ideal specific value can be designated with problems as less as possible.
More preferably, the bit length of the specific value is set as same as the bit number of the output data.
According to this, since the bit length of the specific value is designated to be equal to the bit length of the output data, when the second table input data overflows due to the adding process in the interpolation process, the numerical accuracy of the specific value to be used as its alternative is satisfactorily improved. In particular, when the look-up table for conversion has input/output characteristic data for performing xcex3 conversion of image data, the maximum value of the output range where the output data can lie is best employed as the ideal specific value.
More preferably, the look-up table for conversion has input/output characteristic data for performing xcex3 conversion of image data.
According to this, since the look-up table for conversion has input/output characteristic data for performing xcex3 conversion of image data, it is possible to readily execute xcex3 conversion even with a reduced storage capacity of the look-up table storage memory which heretofore required a large capacity.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.